The size of MOS transistors has been reduced considerably with a trend toward high density, high integration and miniaturization of semiconductor integrated circuit devices. With the miniaturization trend, especially due to the decreasing channel length, hot carrier degradation has been a critical problem, since the degradation will affect the reliability of a MOS transistor. Hot carrier degradation refers to a phenomenon in which highly energized electrons and positive holes (hereinafter ‘hot carrier’) are generated by a high electric field at a drain end of a MOS transistor, which will degrade the characteristics of a gate oxide film. This hot carrier degradation includes plural degradation modes. In degradation under a condition to cause a maximum substrate current or degradation under a condition that the gate voltage Vgs is a half the drain voltage Vds, a drain current is decreased over time for both N-type and P-type MOS transistors. As a result, the delay time of the circuit is increased over time. When the delay reaches a certain degree, a timing error occurs at a time of input/output of signals within the semiconductor integral circuit or between the circuit and outside, and this causes a malfunction of an entire system in which the semiconductor integrated circuit is assembled.
Regarding the hot carrier degradation, hot carrier reliability has been evaluated by a stress acceleration experiment under a DC (direct current) condition with respect to the MOS transistor. Product reliability has been provided by optimizing a production process to satisfy the hot carrier evaluation standard.
A hot carrier lifetime model used in such a hot carrier reliability evaluation is as follows. Hot carrier degradation of a MOS transistor is evaluated by, for example, ΔId/Id, and this is a ratio of a drain current variation ΔId to an initial drain current Id. Under a static hot carrier stress condition by a DC, the hot carrier degradation rate ΔId/Id is represented by the following formula (1).ΔId/Id=A·tn  (1)
Here, ‘t’ denotes a hot carrier stress time, while characters ‘A’ and ‘n’ are regarded as coefficients depending on a transistor manufacturing process and a stress condition.
If a transistor lifetime τ is defined as a stress time required for a variation rate of drain current to reach (ΔId/Id)f, a formula (2) is obtained from the formula (1). For example, time t when (ΔId/Id)f=10% is defined as a lifetime τ.(ΔId/Id)f=A·τn  (2)
In a typical stress acceleration experiment for a MOS transistor, DC stress is applied to a transistor so that the transistor lifetime reaches a variation rate (ΔId/Id)f defined by the formula (2) within a measureable time period, that is, from 1 second to about 100,000 seconds. Then, a drain current of the transistor is measured to calculate a transistor lifetime from ΔId/Id in a linear region or a saturation region.
The following stress voltage application method is used in a stress acceleration experiment during a hot carrier reliability evaluation. Every gate voltage Vg is determined under a condition where the hot carrier degradation rate is maximized with respect to each of plural drain voltages Vd used for the acceleration experiment. In other words, each of the gate voltages Vg causes a maximum substrate current Isub under a respective drain current. At this time, one gate voltage is set for each drain voltage. In this way, a transistor lifetime is calculated under a condition in which the degradation rate is maximized with respect to an arbitrary drain voltage.
A method of evaluating hot carrier reliability of a MOS transistor is described in IEEE Electron Device Lett., vol. 4, pp. 111–113, April 1983 by E. Tanaka et al. According to the description, the lifetime τ of a MOS transistor is calculated by using an empirical model represented by the following formula (3).τ∝exp(−C/Vds)  (3)In this formula, Vds denotes a voltage between a drain and a source, and C denotes a fitting parameter.
Furthermore, a method of evaluating hot carrier reliability of a MOS transistor for a case in which a substrate voltage Vbs is applied is described, for example, in Proc. IEEE VLSI Tchnol. Symp., pp. 119–120, 2001 by E. Murakami et al. According to the description, the lifetime τ of a MOS transistor is determined by using an empirical model represented by the following formula (4).τ∝exp(−C(1/Vds+1/Vdb))  (4)
FIG. 5 shows a method of estimating a lifetime based on this empirical model. In FIG. 5, each of the elements 21 denotes a measured value of the lifetime under a condition to cause a maximum substrate current or under a condition that a gate voltage Vgs=Vds/2, and a line 22 denotes a regression line of lifetime estimation. Numeral 23 denotes a value of 1/Vds+1/Vdb in actual use, and 24 denotes an estimated lifetime in actual use. For a lifetime estimation, 1/Vds+1/Vdb is used to enter a horizontal axis of a graph, and a logarithm of τ is used to enter the vertical axis so that the measured values 21 for a lifetime are plotted. Next, the regression line 22 is fitted to the measured values 21 by using a least squares method. The regression line 22 is used to obtain a lifetime corresponding to the 1/Vds+Vdb in actual use, and this is determined as an estimated lifetime 24 in actual use. Hot carrier reliability evaluation is executed by observing whether the lifetime 24 satisfies a hot carrier evaluation standard, e.g., whether the lifetime 24 satisfies a standard of at least 10 years.
Recently however, such a conventional hot carrier evaluation standard has been difficult to satisfy in the hot carrier reliability evaluation under the DC condition. For solving this problem, a recently developed technique provides product reliability by a simulation of hot carrier degradation for a semiconductor integrated circuit (hereinafter “circuit reliability simulation”). Acircuit reliability simulator simulates a circuit operation subsequent to hot carrier degradation by using a hot carrier lifetime model and a SPICE parameter after degradation, and the simulation is based on calculated values of voltage and current at every terminal of every transistor, which are calculated by a circuit simulator SPICE. Typical simulators are BERT developed at the University of California, Berkeley (R. H. Tu et al., “Berkeley reliability tools-BERT,” IEEE Trans. Compt.-Aided Des. Integrated Circuits & Syst., vol. 12, no. 10, pp. 1524–1534, October 1993), and BTABERT (a commercial version of BERT). This circuit reliability simulation technique is used for estimating degraded or malfunctioning parts in a semiconductor integrated circuit and measures against the degradation or malfunction are taken during designing, so that reliability assurance or reliability design is possible.
An example of simulation methods concerning hot carrier degradation of a MOS transistor is described in IEEE Trans. Electron Devices, vol. 35, pp. 1004–1011, July 1988 by Kuo et al. A hot carrier lifetime model applied to this circuit reliability simulator is as follows. According to Kuo et al., a lifetime τ of a MOS transistor is represented by an empirical formula (5) using a hot carrier lifetime model.τ=((ΔId/Id)f)1/n·H·W·Isub−m·Idm−1  (5)In the formula, W denotes a gate width, H denotes a coefficient depending on a condition for manufacturing a transistor, Isub denotes a substrate current, and m denotes an index relating to an impact ionization and interface level formation.
A coefficient A in a hot carrier lifetime model is represented by a formula (6) that is derived from the formulas (2) and (5).A=((W·H)31 1·Isubm·Id1−m)n  (6)
Therefore, a formula (7) is derived from the formulas (1) and (6).ΔId/Id=((W·H)−1·Isubm·Id1−m·t)n  (7)When Age is defined for convenience as in the following formula (8), the formula (7) can be rewritten into a formula (9).Age=(W·H)−1Isubm·Id1−m·t  (8)ΔId/Id=(Age)n  (9)In the formula (8), ‘Age’ represents a stress quantity from a start of hot carrier stress to a time t in a hot carrier lifetime model. From a physical point of view, it represents a total quantity of hot carrier having an energy of at least a critical energy to generate damage in a MOS transistor.
The parameters n, H and m used in the formulas (4)–(9) are regarded as hot carrier lifetime parameters. These hot carrier lifetime parameters are functions of vertical electric field strength at a drain end where the hot carrier is generated. Therefore, these parameters are represented as functions of a gate-drain voltage Vgd.
FIG. 7 shows a method of simulating characteristics after degradation by using a ΔId model. A simulation method using a ΔId model is described in IEEE Trans. Electron Devices, vol. 40, pp. 2245–2254, December 1993 by Quader et al.
FIGS. 6(A) and 6(B) are equivalent circuit diagrams showing a method of simulating hot carrier degradation of a MOS transistor. In FIGS. 6(A) and 6(B), 25a denotes a fresh MOS transistor before stress application, 25b denotes a MOS transistor after stress application, and 26 denotes a variable current source. FIG. 6(A) shows a drain current Id flowing in a fresh MOS transistor 25a before stress application. FIG. 6(B) shows a drain current Id′ flowing in a MOS transistor 25b after hot carrier degradation. It is shown that the drain current flowing in the transistor changes from the initial drain current Id by ΔId due to the hot carrier degradation.
As shown in the following formula (10), a drain current Id′ after degradation is simulated by adding degradation ΔId of a drain current to a fresh drain current Id before stress application.Id′=Id(Vd, Vg)+ΔId(Age, Vd, Vg)  (10)
ΔId is a function of Age as stress quantity from the start of hot carrier stress to a time t, as well as a function of a drain voltage Vd and a gate voltage Vg. For calculating Age under a dynamic stress condition by AC (alternating current) in a circuit, the formula (8) is rewritten into the following formula (11) as an integral form over time for calculation.Age=∫[(W·H)−1Isubm·Id1−m]dt  (11)In this simulation, ΔId is represented by an equivalent circuit prepared by adding a variable current source 26 shown in FIG. 6(B) to a source-drain of an initial MOS transistor. At this time, a transistor parameter to calculate the initial drain current is not changed.
FIG. 7 is a flow chart to show a process to simulate hot carrier degradation of a MOS transistor according to a conventional technique. In this flow chart, a step S01 includes sub-steps S01a–S01g to extract an unknown parameter in the formulas (10) and (11) with respect to a hot carrier lifetime model by a preliminary measuring experiment.
In the sub-step S01a, a model formula Isub=g(Vg, Vd) is determined to fit to measurement data of plural substrate currents Isub in a preliminary measuring experiment, so that the substrate current Isub in the formula (11) is determined. Here, Vg denotes a gate voltage, and Vd denotes a drain voltage. An example of a method for determining a substrate current Isub is described in IEEE Electron Device Lett., vol. EDL-5, pp. 505–507, December 1984 by Chan et al.
The sub-steps S01b–S01d are for extracting hot carrier lifetime parameters in a preliminary measuring experiment. In the sub-step S01b, a stress voltage is applied to a MOS transistor, and a hot carrier lifetime defined by the formula (2) is measured. For applying the stress voltage, a gate voltage Vg is set so that a gate-drain voltage Vgd=Vg−Vd is constant with respect to plural drain voltages Vd. In this method, typically plural numbers of Vgd are set, and also gate voltages Vg=Vd+Vgd corresponding to the plural Vgd are set with respect to every drain voltage Vd. In the following sub-step S01c, coefficient n is extracted as a function of Vgd by a comparison between the empirical formula (1) and data concerning measurement points in a DC stress experiment for the sub-step S01b. Similarly in the sub-step S01d, an index m and a coefficient H are extracted as functions of Vgd by a comparison between the empirical formula (5) and data concerning measuring points in a DC stress experiment for the sub-step S01b. 
Sub-steps S01e–S01g are for determining a fresh drain current Id before stress application and degradation ΔId of the drain current in the formula (10) for a ΔId model. In the sub-step S01e, transistor parameters such as carrier mobility and a flat-band voltage are extracted. Such parameters are used for determining fresh drain current Id(Vd, Vg) before stress application. BSIM (Berkeley Short-Channel IGFET Model) is used for a model to determine such a fresh drain current Id(Vd, Vg). The BSIM is described in detail in IEEE J. Solid-State Circuits, vol. SC-22, pp. 558–566, August 1987 by Sheu et al. Subsequently in the sub-step S01f, DC stress is applied to the transistor. In the sub-step S01g, ΔId model parameters are extracted before and after the DC stress application. The drain current degradation ΔId(Age, Vd, Vg) is determined by the ΔId model parameters. The ΔId model is described by Quader et al. in relation to NMOS. PMOS is described in JP-A-08–64814 by Shimizu et al.
The transistor parameters should be extracted before DC stress application so that actual transistor characteristics before the stress application coincide with simulated transistor characteristics. The ΔId model parameters should be extracted before and after the DC stress application so that the actual drain current degradation ΔId before and after the stress application coincides with the simulated drain current degradation ΔId.
The step S02 includes sub-steps S02a–S02d so that a reliability simulator simulates hot carrier degradation of a transistor in accordance with parameters extracted in the step S01 and also with the formulas (10) and (11).
In the sub-step S02a, a drain current is simulated by transistor parameters before stress application, where the parameters have been extracted in the prior sub-step S01e. In the sub-step S02b, a substrate current is simulated on the basis of a substrate current model formula Isub=g(Vg, Vd) determined by the S01a. In the sub-step S02c, Age, which represents degradation of each transistor based on the formula (11), is calculated by time-integrating functions of a drain current Id and a substrate current Isub in a circuit. At this time, the drain current Id simulated in the sub-step S02a, the substrate current Isub simulated in the sub-step S02b, and hot carrier lifetime parameters H and m calculated in the sub-step S01d, are used. In the sub-step S02d, hot carrier degradation of the transistor is simulated by using the formula (10) on the basis of the Age.
The following is a detailed explanation of a method of extracting hot carrier lifetime parameters H and m for a hot carrier lifetime model. FIG. 8 is an explanatory view of a method of extracting hot carrier lifetime parameters H and m. FIG. 8 relates to a plot for calculating hot carrier lifetime parameters H and m included in the empirical formula (5) using a hot carrier lifetime model. In FIG. 8, the vertical axis is a logarithmic scale of a value τ·Id/W calculated from a lifetime τ in a DC stress experiment, a drain current Id during a stress and a gate width W of a MOS transistor. The horizontal axis is a logarithmic scale of a ratio Isub/Id when Isub is a substrate current during a stress and Id is a drain current. Numeral 27 denotes data concerning a plurality of measurement points in a DC stress experiment, and 28 denotes a line fitted with respect to data concerning the measurement points. The MOS transistor lifetime τ is measured under plural gate-drain voltage Vgd conditions, e.g., under three conditions of Vgd=0.0, −1.0, and −2.0 V, so that data 27 for plural measurement points are obtained. A line 28, fitted by a least squares method with respect to data 27 concerning the measurement points, is obtained. Hot carrier parameters H and m are obtained respectively from an intercept and a gradient of the line 28. By executing this method for plural Vgd, the hot carrier lifetime parameters H and m in a hot carrier lifetime model can be calculated as functions of Vgd.
The above description is about a conventional method of estimating a lifetime of hot carrier degradation of a MOS transistor, and a conventional method of simulating degradation in circuit characteristics caused by the hot carrier degradation. However, these methods can cause the following problems.
First, in the method of estimating a lifetime of hot carrier degradation of a MOS transistor, the model formula (4) adopting an effect of a substrate voltage lacks explicit physical grounds, and the repeatability will not be assured. Secondly, since a lifetime is represented as a function of a drain voltage and a substrate voltage, the lifetime cannot be predicted accurately with respect to an arbitrary gate voltage.
A third problem is that a lifetime under a condition in which a hot carrier degradation rate is maximized will be estimated as longer than its actual lifetime. Therefore, depending on use conditions, the lifetime in actual use of the MOS transistor may be shorter than the lifetime estimated corresponding to this model. That is, the quality of the product cannot be assured appropriately.
Regarding the method of simulating circuit characteristic degradation caused by the hot carrier degradation, the effect of the substrate voltage with respect to the hot carrier degradation is not included in the conventional hot carrier lifetime model represented by the formula (5). According to the formula (4), the lifetime will be shortened in comparison with the conventional hot carrier lifetime model formula (5) when a substrate voltage is applied. Therefore, in a case of applying a substrate voltage, the lifetime in actual use will be shorter than the simulation result obtained by using the conventional model formula (5). However, as described above, the model formula (4) cannot be used for the simulation of the circuit characteristic degradation, due to a lack of repeatability based on physical grounds and gate voltage dependency.
The conventional model formula (5) is based on a hypothesis that hot carrier degradation occurs due to one kind of hot carrier, that is electrons or holes, having an energy of not lower than the critical energy required for causing damage on the MOS transistor, and that the hot carrier lifetime is inversely proportional to the yield of this one kind of hot carrier. According to this model, it is difficult to provide a hot carrier lifetime model adopting a physical effect with respect to the hot carrier degradation in the substrate voltage.